VSI OpenVMS E9.2-4 for x86-64 is now available in field test as part of our ongoing commitment to modernizing OpenVMS on the industry-standard CPU architecture.
VMS Software, Inc. has migrated OpenVMS and its layered products to the industry standard x86-64 architecture to help customers protect their investment in OpenVMS infrastructure, especially in virtualized environments and in the cloud. This field test release of OpenVMS E9.2-4 is available for porting, development, testing and evaluation use on x86-64. Its main focus is on enhancements for virtualization, performance, and security, while also addressing issues found since V9.2-3.
To determine if the CPU in your system provides the features required to run OpenVMS V9.2-1 or later, run this Python script. Information on the virtual machine hosts tested by VSI is provided in the release notes.
The use of a Cluster-Common System Disks is not recommended with OpenVMS E9.2-4, because of a system disk integrity issue that was discovered just prior to the field test release. We plan to release an updated field test kit to address this issue.
Check lists of open-source and layered products that work with OpenVMS here (filter by architecture to see those available on x86).
Main New Features
- iSCSI support: Allows OpenVMS to use iSCSI targets as shared data disks in a cluster, removing the dependency on dedicated Fibre Channel hardware.
- PVSCSI support: Allows OpenVMS to use paravirtualized SCSI controllers on VMware ESXi, offering increased disk I/O performance.
- Secure Boot support and Signed System Images: Offers increased system security by requiring that all system images are signed with a valid signature, preventing tampering.
- Native build: Starting with E9.2-4, OpenVMS is built with native, optimizing compilers, raising the overall performance of the system.
Documentation
CPU Requirements
- Intel or AMD x86 CPU
- 64-bit Instruction set
- NX processor bit (NX)
- Streaming SIMD Extensions 4.1 (SSE4.1)
- Virtualization Technology (VT-x/AMD-V)
- XSAVE instructions
- Time Stamp Counter (TSC)
- Advanced Programmable Interrupt Controller (APIC)
- Memory Type Range Registers (MTRR)
Most Intel CPUs from 2016/AMD (Zen) CPUs from 2017 and later support these processor features.
Optional Features:
- Process-Context Identifier feature (PCID)
- Extended Advanced Programmable Interrupt Controller (x2APIC)
- XSAVEOPT instruction
- FSGSBASE instructions
- Microarchitectural Data Sampling Mitigation (MD_CLEAR)
Tested Platforms
Refer to the Release Notes for a list of hypervisors on which this release has been tested.
For the previous release info, refer to this page.
Questions?
Check out our x86 Port Q&A or contact us.